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rev. 1.0 10/12 copyright ? 2012 by silicon laboratories CP2114 CP2114 s ingle -c hip usb a udio to i2s d igital a udio b ridge single-chip usb audio to i2s digital audio bridge ?? usb hid to i2c to co mmunicate with dac/codec ?? supports usb hid consumer controls for volume and mute synchronization ?? integrated usb transceiver ; no external resistors required ?? integrated clock; no external crystal required ?? integrated one-time programmable rom for product customization ?? on-chip voltage regulator: 3.45 v output supports a wide range of codecs/dacs ?? out-of-box support for three major codecs/dacs ?? internal programmable memory supports additional codec/dac configurations usb audio class v1.0 support ?? i2s master mode, i2s and left justified pcm outputs ?? supports 48 khz,16-bit stereo digital audio ?? no custom driver required ?? supports windows 7, vista, xp, mac os-x, linux ?? supports ipad/ios (with usb camera kit connector) ?? open access to inte rface specification usb peripheral function controller ?? usb specification 2.0 compliant; full-speed (12 mbps) ?? usb suspend states supported via suspend pins usb hid to uart auxi liary communication interface ?? apis for quick application development ?? supports windows 7, vista, xp, server 2003, 2000 ?? supports mac os-x 12 configurable gpio pins with alternate functions ?? usable as inputs, open-drain or push-pull outputs ?? uart signals, audio playback controls, dac select pins ?? configurable clock output ?? toggle leds upon uart transmission or reception supply voltage ?? self-powered: 3.0 to 3.6 v ?? usb bus powered: 4.0 to 5.25 v ?? i/o voltage: 1.8 v to v dd package ?? rohs-compliant 32-pin qfn (5 x 5 mm) ordering part number ?? CP2114-b01-gm temperature range: ?40 to +85 c figure 1. example system diagram connect to vbus or external supply vbus d+ d- gnd usb connector logic level supply (1.8v to vdd) uart CP2114 data fifos internal oscillator 256 b rx 256 b tx uart controller usb interface peripheral function controller full-speed 12 mbps transceiver 352 byte prom (usb customization) voltage regulator baud rate generator regin vdd gnd vio vbus d+ d- i/o power and logic levels rst gpio.10_tx gpio.11_rx vpp volume/mute controls gpio and suspend controller suspend signals gpio.0_rmute gpio.1_pmute gpio.2_vol+ gpio.3_vol- gpio.4_rmuteled gpio.5_txt_dacsel0 gpio.6_rxt_dacsel1 gpio.9_clkout suspend suspend i2s and i2c signals to codec/dac audio controller sda scl mclk sck lrck sdin sdout extclk support for 32 audio codec//dac configurations 5.5 kbyte prom (audio customization) gpio.7_rts_dacsel2 gpio.8_cts_dacsel3 codec/dac selector clock output (optional) clock input (optional) wm8523 configuration pcm1774 configuration cs42l55 configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 2 rev. 1.0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 3 t able of c ontents section page 1. system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. pinout and package defini tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. qfn-32 package specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. audio (i2s and i2c) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.1. one-time programmable rom configuration programming . . . . . . . . . . . . . . . . . . 18 5.2. real-time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3. CP2114 i2s and left -justified digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4. usb and digital audio clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5. usb audio synchronization modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6. CP2114 clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. usb function controller and transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. asynchronous serial data bus (uart) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. gpio pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1. gpio.0-4?audio playback and record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2. gpio.5-8?dac selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3. gpio.5-6?uart transmit and rece ive toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4. gpio.7-8?hardware flow contro l (rts and cts) . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.5. gpio.9?clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. one-time programmable rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1. audio interface configurat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2. usb and gpio conf iguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 10. voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11. CP2114 interface specification a nd windows interface dll . . . . . . . . . . . . . . . . . . . . 42 12. relevant application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 4 rev. 1.0 1. system overview all major commercial operating systems (windows, linux , mac, ios) support the standard usb audio device class. codecs and dacs typically have only an i2s (int er-ic sound) digital interface, and thus cannot connect directly to a host system. in addition, when a dac is powered on, it typically ne eds to be configured by the host via an i2c (inter-integrated-circuit) digi tal interface, with a non-standard protocol. finally, in order to support push button volume and mute synchronization with the host system, the target usb device must support the standard usb-hid consumer control interface. thus, adding usb di gital audio to an embedded system or as dongle or appliance typically involves complex usb protocol progr amming as well as i2s and i2c programming capability, prototyping, integration and testing. the CP2114 usb audi o bridge is specifically de signed to overcome all these issues and commoditize usb audio and dac co nfiguration for turn-key product development. note: use with an ipad requires a camera kit connector to get usb from the apple 30-pin connector. usb audio is not sup- ported on the iphone. the CP2114 includes a usb 2. 0 full-speed function controlle r, usb transceiver, oscilla tor, one-time programmable read-only memory (rom), i2s (audio) interface, i2c (con trol) interface, and uart interface in a compact 5 x 5 mm qfn-32 package (sometimes called ?mlf? or ?mlp?). the one-time programmable rom on the device may be used to customize both product informat ion (including usb fields such as ve ndor id, product id, strings, etc...) and external dac configuration strings. by defa ult, the CP2114 provides the following features ?? enumerates to the host as a standard usb audio device and hid consumer control supporting: ?? usb digital audio out (audio playback device) ?? usb digital audio in (microphone/recording device) ?? hid consumer control handling standard volume and mute functionality ?? pre-configured support for 3 commercial dacs ?? handles all i2c configuration of the dac automatically at boot ?? handles all volume and mute traffic converting from usb to i2c messages to the dac ?? tested for usb plug & play and audio quality on all major operating systems ?? uart interface using standard usb hid device class which is natively supported by most operating systems ?? no custom driver installation needed ?? windows and mac dlls provided and interface specific ation is available for development on any operating system ?? implements transmit (tx), receive (rx) , hardware flow control (cts, rts) ?? baud rate support from 300 to 1 mbps, support for 5-8 data bits, 5 parity options, 3 types of stop bits ?? note: the CP2114 devices will not enumerate as a standard hid mouse or keyboard. ?? 12 gpio signals which support alternate functions ?? volume control, uart transmit and receive, uart har dware flow control, uart transmit/receive toggle, configurable clock output, and dac selection ?? support for i/o interface voltages down to 1.8 v is provided via a v io pin. an evaluation kit for the CP2114 (part number: CP2114ek) is available. it includes a CP2114-based usb-to-audio motherboard, a usb cable, and full documentation. addi tional kits with daughter cards are available as well: ?? CP2114-cs42l55 evaluation kit (part number: CP2114-cs42l55ek) includes: ?? CP2114 usb-to-i2s digital audio motherboard ?? cirrus logic cs42l55 codec daughter card ( includes a 3.5mm male-to-male audio cable) ?? CP2114-wm8523 evaluation kit (part number: CP2114-wm8523ek) ?? CP2114 usb-to-i2s digital audio motherboard ?? wolfson microelectronics wm8523 dac daughter card ?? CP2114-pcm1774 evaluation kit (part number: CP2114-pcm1774ek) ?? CP2114 usb-to-i2s digital audio motherboard ?? texas instruments pcm1774 dac daughter card all kits with daughter cards include a usb cable, ear bud headphones, and full documentation. contact a silicon labs sales representatives or go to www.silabs.com to order a CP2114 evaluation kit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 5 2. electrical characteristics table 1. global dc electrical characteristics v dd = 3.0 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter condition min typ max unit digital supply voltage (v dd ) 3.0 ? 3.6 v digital port i/o supply voltage (v io )1.8?v dd v digital supply current (usb active mode) 1 bus powered mode self powered mode with regulator enabled self powered mode with regulator disabled ?1828ma digital supply current (usb suspend mode) 1 bus powered mode self powered mode with regulator enabled ? 750 940 a self powered mode with regulator disabled ? 0.99 1.2 ma supply current - usb pull-up 2 ? 200 228 a specified operating temperature range ?40 ? +85 c notes: 1. if the device is connected to the usb bus, the usb pull-up current should be added to the supply current for total supply current. 2. the usb pull-up supply current values are ca lculated values based on usb specifications. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 6 rev. 1.0 table 2. i2s, i2c, uart and suspend i/o dc electrical characteristics v dd = 3.0 to 3.6 v, v io = 1.8 v to v dd , ?40 to +85 c unless otherwise specified. parameters condition min typ max unit output high voltage (v oh )i oh =?10a i oh =?3ma i oh =?10ma v io ?0.1 v io ?0.2 ? ? ? v io ?0.4 ? ? ? v output low voltage (v ol )i ol =10a i ol =8.5ma i ol =25ma ? ? ? ? ? 0.6 0.1 0.4 ? v input high voltage (v ih ) 0.7 x v io ??v input low voltage (v il )??0.6v input leakage current weak pull-up off weak pull-up on, v io = 0 v ? ? ? 25 1 50 a maximum input voltage open drain, logic high (1) ? ? 5.8 v table 3. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter condition min typ max units rst input high voltage 0.75 x v io ??v rst input low voltage ? ? 0.6 v minimum rst low time to generate a system reset 15 ? ? s table 4. voltage regulator electrical specifications ?40 to +85 c unless otherwise specified. parameter condition min typ max unit input voltage range 3.0 ? 5.25 v output voltage output current = 1 to 100 ma* 3.3 3.45 3.6 v vbus detection input threshold 2.5 ? ? v bias current ? ? 120 a *note: the maximum regulator supply current is 100 ma. this includes the supply current of the CP2114 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 7 table 5. gpio output specifications ?40 to +85 c unless otherwise specified. parameter condition min typ max unit gpio.9 clock output f out x 0.985 f out f out x 1.015 hz tx toggle rate ? 20 ? hz rx toggle rate ? 20 ? hz table 6. one time programming specifications v dd = 3.3 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter condition min typ max unit digital port i/o supply voltage (v io ) during programming 3.3 v dd v capacitor on v pp for programming ? 4.7 ? f table 7. system clock specifications v dd = 3.3 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter condition min typ max unit internal oscillator sf = 0 (reg ister: system_props, bit: 1) sf = 1 (register: system_props, bit: 1) ? ? 48 49.152 ? ? mhz mhz external cmos clock input frequency sf = 0 (register: system_props, bit: 1) sf = 1 (register: system_props, bit: 1) 47.880 ? 48 49.152 48.120 ? mhz mhz 1. depending on the requirements of the external dac, the syst em clock frequency will be either 48.0 or 49.152 mhz. see section 5.6 for more information. 2. the usb specification requires a clock accuracy of 0.25%. table 8. i2s digital audio interface specifications v dd = 3.3 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter condition min typ max unit resolution (analog output) ? 16 ? bits resolution (analog input) ? 15 ? bits mclk frequency (sysclk = 48 mhz) ? 12 ? mhz (sysclk = 49.152 mhz) ? 12.288 ? mhz lrck frequency ? 48 ? khz sck frequency (sysclk = 48 mhz) ? 3.429 ? mhz (sysclk = 49.152 mhz) ? 3.511 ? mhz mclk/lrck jitter scs = 0 (external si500s clock) (register: system_props, bit: 2) ?20?ps rms* scs = 1 (internal oscillator) (register: system_props, bit: 2) ?140?ps rms* *note: measurement bandwidth: 100 hz ?40 khz. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 8 rev. 1.0 table 9. i2c specifications v dd = 3.3 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter condition min typ max unit scl frequency i2c_ck = 0 (register: audio_props, bit: 5) i2c_ck = 1 (register: audio_props, bit: 5) ? ? 400 100 ? ? khz table 10. analog output/input characteristics (cs42l55 daughter card) 25 c, bus-powered, usb synchronization mode: asynchronous, digi tal audio interface mode: i2s, dac/adc gains set to 0 db, test signal for analog output: uncompressed wav file, full-scale sine wave at 997 hz, measurement bandwidth 20 hz to 20 khz additional parameters that apply to this table are as follows: ? va = vcp = vldo = 2.5 v ? internal oscillator mode parameter condition min typ max unit analog output (line output) thd + noise 0 db input -20 db input -60 db input ? ? ? ?80 ?91 ?91 ? ? ? db db db dynamic range a-weighted ? 92 ? db noise level output muted ? ?112 ? db frequency response 20 hz - 20 khz ? +0.03, ?0.07 ?db analog input thd + noise -1 db input -20 db input -60 db input ? ? ? ?85 ?87 ?87 ? ? ? db db db dynamic range a-weighted ? 90 ? db noise level analog input locally muted ? 0* ? db *note: when analog input is locally muted, the CP2114 transmits sample values of 0 to the host. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 9 table 11. analog output characteristics (wm8523 daughter card) 25 c, bus-powered, usb synchronization mode: asynchronous, digi tal audio interface mode: i2s, dac/adc gains set to 0 db, test signal for analog output: uncompressed wav file, full-scale sine wave at 997 hz, measurement bandwidth 20 hz to 20 khz additional parameters that apply to this table are as follows: ? linevdd = avdd = 3.3v ? internal oscillator mode ? external headphone amplifier disconnected, no lowpass filter on linevoutl/linevoutr parameter condition min typ max unit thd + noise 0 db fs input ?20 db fs input ?60 db fs input ? ? ? ?83 ?91 ?91 ? ? ? db db db dynamic range a-weighted ? 94 ? db noise level output muted ? ?99 ? db frequency response 20 hz?20 khz ? +0.04, ?0.05 ?db www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 10 rev. 1.0 figure 2. wm8523 frequency response (0 db fs) figure 3. wm8523 thd+n vs. frequency (0 db fs) www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 11 figure 4. wm8523 thd+n vs. amplitude (997 hz) table 12. analog output/input characteristics (pcm1774 daughter card) 25 c, bus-powered, usb synchronization mode: asynchronous, digi tal audio interface mode: i2s, dac/adc gains set to 0 db, test signal for analog output: uncompressed wav file, full-scale sine wave at 997 hz, measurement bandwidth 20 hz to 20 khz additional parameters that apply to this table are as follows: ? vio = vdd = vcc = vpa = 3.3 v. ? aout_l and aout_r outputs have 4.7 ? series resistors. ? internal oscillator mode. parameter condition min typ max unit thd + noise 0 db fs input ?20 db fs input ?60 db fs input ? ? ? ?82 ?89 ?89 ? ? ? db db db dynamic range a-weighted ? 89 ? db noise level output muted ? ?103 ? db frequency response 20 hz - 20 khz ? +0.04, ?0.11 ?db www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 12 rev. 1.0 table 13. absolute maximum ratings parameter condition min typ max unit ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst , gpio, i2s, i2c, or uart pins with respect to gnd v io > 2.2 v v io < 2.2 v ?0.3 ?0.3 ? ? 5.8 v io + 3.6 v voltage on v dd or v io with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd , v io , and gnd ? ? 500 ma maximum output current sunk by rst or any i/o pin ? ? 100 ma note: stresses above those listed may cause permanent damage to t he device. this is a stress rating only, and functional operation of the devices at or exceeding the conditions in th e operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 13 3. pinout and p ackage definitions table 14. CP2114 pin definitions name pin # type description vdd 7 power in power out power supply voltage input. voltage regulator output. see section 10. vio 6 power in i/o supply voltage input. gnd 3 ground. must be tied to ground. rst 10 d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by dr iving this pin low for the time specified in table 3. regin 8 power in 5 v regulator input. this pin is the input to the on-chip voltage regulator. vbus 9 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. d+ 4 d i/o usb d+ d? 5 d i/o usb d? vpp 21* special connect a 4.7 f capacitor between this pin and ground to support one-time programming via the usb interface. suspend 17* d out this pin indicates whether the devi ce is in the usb suspend or not (active- low). suspend 18* d out this pin indicates whether the device is in the usb suspend or not (active- high). sck 2 d out serial clock output signal for the i2s interface. sdin 1 d in serial data input signal for the i2s interface. sdout 32 d out serial data output signal for the i2s interface. mclk 25 d in master clock input for the i2s interface. lrck 23 d out left-right clock output for the i2s interface. extclk 31* d in external clock input of CP2114 ( optional). an external clock is needed if the codec/dac does not support a 12 .000 mhz master clock (mclk). sda 27 d i/o serial data signal for the i2c interface. scl 26 d i/o serial clock signal for the i2c interface. gpio.0 rmute 30* d i/o d in user-configurable input or output. record mute: toggles record between mute and un-mute each time this pin is driven low. gpio.1 pmute 29* d i/o d in user-configurable input or output. playback mute: toggles playback betw een mute and un-mute each time this pin is driven low. *note: pins can be left unconnected when not used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 14 rev. 1.0 gpio.2 vol- 14* d i/o d in user-configurable input or output. decreases volume ea ch time this pin is driven low. gpio.3 vol+ 13* d i/o d in user-configurable input or output. increases volume ea ch time this pin is driven low. gpio.4 rmuteled 12* d i/o d out user-configurable input or output. record mute led: this pin is dr iven low while re cording is muted. gpio.5 txt dacsel0 28* d i/o d out d in user-configurable input or output. this pin toggles while the uart is transmitting data and is logic high when the uart is not transmitting data. selects one of the predefined dacs. see section 8.2 for more information. gpio.6 rxt dacsel1 11* d i/o out d in user-configurable input or output. this pin toggles while the uart is receiving data and is logic high when the uart is not receiving data. selects one of the predefined dacs. see section 8.2 for more information. gpio.7 rts dacsel2 19* d i/o d out d in user-configurable input or output. ready to send control output (act ive low) for the uart interface. selects one of the predefined dacs. see section 8.2 for more information. gpio.8 cts dacsel3 20* d i/o d in d in user-configurable input or output. clear to send control input (activ e low) for the uart interface. selects one of the predefined dacs. see section 8.2 for more information. gpio.9 clkout 22* d i/o d out user-configurable input or output. outputs a configurable frequency clock signal. gpio.10 tx 16* d i/o d out user-configurable input or output. asynchronous data output (uart transmit) for the uart interface. gpio.11 rx 15* d i/o d in user-configurable input or output. asynchronous data input (uart receive) for the uart interface. nc 24* this pin should be left unconnected or tied to v io. table 14. CP2114 pin definitions (continued) name pin # type description *note: pins can be left unconnected when not used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 15 figure 5. qfn-32 pinout diagram (top view) 17 25 mclk 16 8 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 gnd (optional) CP2114-gm top view scl sda gpio.5_txt_dacsel0 gpio.1_pmute gpio.0_rmute extclk sdout sdin sck gnd vdd d- vio gpio.4_rmuteled gpio.3_vol+ gpio.2_vol- gpio.11_rx gpio.10_tx suspend suspend gpio.7_rts_dacsel2 gpio.8_cts_dacsel3 vp p gpio.9_clkout lrck nc regin gpio.6_rxt_dacsel1 d+ rst vbus www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 16 rev. 1.0 4. qfn-32 package specifications figure 6. qfn-32 package drawing table 15. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 e2 3.20 3.30 3.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 5.00 bsc. aaa ? ? 0.15 d2 3.20 3.30 3.40 bbb ? ? 0.10 e 0.50 bsc. ddd ? ? 0.05 e 5.00 bsc. eee ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 17 figure 7. qfn-32 recommended pcb land pattern table 16. qfn-32 pcb land pattern dimensions dimension min max dimension min max c1 4.80 4.90 x2 3.20 3.40 c2 4.80 4.90 y1 0.75 0.85 e 0.50 bsc y2 3.20 3.40 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 3x3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the center ground pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 18 rev. 1.0 5. audio (i2s and i2c) interfaces the i2c interface configures the dac to output sound and th e i2s interface provides the digital audio stream to the dac. in addition to full-featured off the shelf functionalit y, the CP2114 can be customized in two ways; via one-time programmable rom configuration and a real-time api. 5.1. one-time programmable rom configuration programming the CP2114 has 5.5kb of on board one-time programmabl e rom available to store up to 29 different custom configurations. three of the 32 slots are preprogrammed configurations. the configurations can be selected as boot configurations and will automatically configure the CP2114 and the i2c connected dac when the CP2114 is powered on. alternatively the custom configurations can be assigned to a dac select pin selection. the boot configuration is then selected by pi n-strapping the dac select pins. silicon labs provides a pc gui application to program the configuration to the CP2114 one-time programmable rom. the CP2114 can be programmed on a production line or a conf iguration file can be provided to silicon labs and pre-pr ogrammed parts can be supplied directly by silicon labs. 5.2. real-t ime programming the CP2114 presents the host with a usb hid interface which can be used to send messages directly to the CP2114 for internal configuration or directly to the dac ov er the i2c interface. this pr ovides real-time configuration changes to the CP2114 and dac via host program control. in addition, the usb hid pipe can be used to write and read to the CP2114 gpio pins as desired. 5.3. CP2114 i2s and left -justified digital audio the CP2114 supports ?i2s? and ?left justified? digital audi o formats. note that the di fference in the two modes is that for the i2s format, the msb of the data streams (sdout and sdin) are delayed by one clock (sck) cycle after the channel clock (lrck) transitions as compared to the left justified format. the digital audio format can be configured in the CP2114 one-time programmable rom. figure 8 shows the signals in i2s format, and figure 9 shows the signals in left justified format. figure 8. i2s format msb -1 -2 +2 +1 lsb msb -1 -2 +2 +1 lsb left channel right channel lrck sck sdout sdin msb -1 -2 +2 +1 lsb msb -1 -2 +2 +1 lsb mclk www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 19 figure 9. left-justified format mclk : master clock. this is a high frequency clock to the dac used for the digital to analog conversion process within the dac. this clock will be a mu ltiple of the lrck going to the dac. typically mclk = 250*lrck or mclk=256*lrck. lrck : left-right clock. this is used to synchronize the dac audio data wo rd timing with the CP2114 audio data word timing (i.e. edges are used to synchronize the beginning of the left and right audio samples). sck : bit synchronization clock (also called bclk). this prov ides a timing signal used by the dac to latch the audio output data bits on sdout and asse rt the audio input data bits on sdin. sdout : audio-out data stream going to the dac. sdin : audio-in data stream coming from the dac. note: mclk, lrck, sck and sdout are driven by the CP2114. sdin is driven by the dac. the CP2114 supports only 48 khz, 16 bit digital audio. this is typically not an issue for source usb audio as the device capabilities are reported to the host and any sample ra te conversion (for say 44.1 khz audio) is done automatically by the host. some dacs however may require 24 bit digital audio data on the i2s data stream. in this case, the CP2114 will send the useful 16 bit audio to the dac on sdout in t he most significant 16 bits and pad the remaining 8 bits of data with 0s. likewise the CP2114 will read the msb 16 bits of data on din and throw out the lsb 8 bits from sdin. the CP2114 can be configured in 16 bit or 24 bit mode via a configuration option in the CP2114 one-time programmable rom. 5.4. usb and digital audio clock requirements the CP2114 supports a number of clock configurations allowing support for a variety of dacs and associated clocking options to optimize cost and qua lity. the two clocks of consideration are: usb clock : full speed usb requires devices have a 12 mhz clo ck with tolerance of 0.25%. this means the usb device (CP2114) must maintain its usb clock in the ra nge of 11.97 mhz < usb clock < 12.03 mhz. this range is supported by the CP2114 which also has built-in usb clo ck recovery. however, it does have implications on the audio dac. digital audio clock (mclk) : dacs typically require that mclk must be a multiple of lrck, and this multiple is typically required to be 250 or 256 (or some sub or super mu ltiple of these values). given an audio sample rate of lrck = 48 khz, the resulting mclk requirement is shown in equation 1 or equation 2. equation 1. digital audio clock (mclk) frequency for a multiple of 250 equation 2. digital audio clock (mclk) frequency for a multiple of 256 msb -1 -2 +2 +1 lsb msb -1 -2 +2 +1 lsb left channel right channel lrck sck sdout sdin msb -1 -2 +2 +1 lsb msb -1 -2 +2 +1 lsb -3 -3 -3 -3 mclk mclk 250 48 khz = 12.000 mhz ? = mclk 256 48 khz = 12.288 mhz ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 20 rev. 1.0 a dac accepting a multiple of 250 is thus compatible with usb clock requirements, whereas a dac requiring a 256 multiple is fundamentally incomp atible with usb clock requirements. in this case, generally one clock is needed for usb and another clock is needed for audio. the CP2114 supports a variety of configurations to address this issue and is co vered in section 5.6. 5.5. usb audio sy nchronization modes the usb standard defines synchronization relative to sour ce and sinks. for audio-out, the host is the source and the device is the sink. for audio-in, the device is the source and the host is the sink. usb defines modes which govern the operation of sources and sinks according to the following table. the CP2114 supports asynchronous and synchronous modes. table 17. usb audio synchronization modes mode source sink asynchronous free running clock provides implicit feedforward to the sink free running clock provides explicit feedback to the source synchronous clock locked to usb sof uses implicit feedback clock locked to the usb sof uses implicit feedback adaptive clock locked to sink uses explicit feedback clock locked to the data flow uses implicit feedback notes: 1. implicit feedforward means the recipient determines the next data input size according to the current input size (i.e. if 48 samples were sent in the current frame then expect th e same number in the next frame). 2. explicit feedback means the recipient of the feedback will receive an explicit request for the number of samples to send in the next frame. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 21 5.6. CP2114 cl ock configuration the CP2114 always reports its capabilitie s to the usb host at a sample rate of 48 khz and sample size of 16 bits. for source audio files differ ing from this format the u sb host will automatically perfor m sample rate conversion. the CP2114 has the following configuration options: table 19 shows all possible clock configuration settings for the CP2114. the CP2114 divides the usb source clock by 4 so a clock of 48mhz provides the 12 mhz clock nee ded for usb. the CP2114 divides the system clock by 4 to derive mclk. so a 48 mhz system cl ock will generate mclk=12 mhz. if the CP2114 is configured to operate in asynchronous mode, it will automatically use explicit feedback to the host. if it is configur ed for sy nchronous mode, then the sample synchronization method is note d in the table. there are a number of invalid clocking configurations that result from either the usb clo ck not resulting in 12 mhz or the mclk/lrck not being an integer divisor. operating in asynchronous mode is recommended because it best accommodates any mismatch in host/CP2114 clocks. oper ating in synchronous mode requ ires the CP2114 to adjust its internal oscillator to match the host sample rate, or to periodically drop or repeat an audio sample if sysclk is driven by an external clock. table 18. clock configuration options configuration parameter options stream type asynchronous synchronous usb clock source internal external system clock source internal external system clock frequency 48 mhz 49.152 mhz mclk/lrck ratio 250 256 table 19. valid clock configuration modes mode usb clock (usbclk) source system clock (sysclk) source int freq (mhz) mclk/ lrck ratio ext osc freq (mhz) notes 1 int int 48 250 na ? lowest cost - no external clock required ? dac must support 12.0 mhz mclk ? sync mode: intosc adjusted to accommodate clock mismatch 2 int ext 48 256 49.152 ? async mode: best audio quality ? sync mode: must drop/repeat samples to accommodate clock mismatch 3 ext int 48 49.152 250 256 48 ? intosc frequency dictated by dac mclk/ lrck ratio ? sync mode: intosc adjusted to accommodate clock mismatch 4ext ext 4825048 ? dac must support 12.0 mhz mclk ? async mode: best audio quality ? sync mode: must drop/repeat samples to accommodate clock mismatch www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 22 rev. 1.0 figure 10 shows the clocking scheme, with the c onfigurable options shown in darker boxes. ?? the usb clock frequency must always be 12mhz whether using the inte rnal or an external oscillator. ?? mclk is sysclk/4 and so will be 12mhz or 12.288mhz (as determined by the dac clock requirement). ?? lrck is mclk divided by 250 or 256 in order to get the correct 48 khz sample rate conversion. ?? for mclk = 12.288 mhz, the lrck divisor must be 256. ?? for mclk = 12.000 mhz, the lrck divisor must be 250. ?? lrck gates sck and sck is driven at sysclk / 14. ?? sck is the clock for sdout and sdin. figure 10. clock configuration block diagram the particular setting for configurat ion 1 (usb and sysclk = inte rnal frequency of 48 mh z, mclk/lrck divisor = 250) is shown in figure 11. figure 11. configuration 1 example lrck sck sdout sdin mclk cmos oscillator 48mhz/ 49.152mhz usb block mclk internal oscillator 48mhz/49.152 4 lrck sck sdout sdin audio out buffer audio in buffer usb sysclk 4 250/256 14 msb -1 msb -1 nc lrck sck sdout sdin mclk usb block mclk internal oscillator 48mhz 4 lrck sck sdout sdin audio out buffer audio in buffer usb sysclk 4 14 msb -1 msb -1 250 www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 23 6. usb function controller and transceiver the universal serial bus (usb) function controller in the CP2114 is a usb 2.0 compliant full-speed device with integrated transceiver and on-chip matching and pullup resistors. the usb function controller manages all control, audio, and uart transfers between the usb and the CP2114. the usb suspend and resume modes are supported for pow er management of bot h the CP2114 device as well as exte rnal circuitry. the CP2114 will enter suspend mode when suspend signaling is detected on th e bus. on entering suspend mode, the suspend signals are asserted. the suspend signals are also asserted af ter a CP2114 reset until device configuration during usb enumeration is complete. the suspend pin is logic high when the device is in the suspend state, and logic low when the device is in th e normal mode. the suspend pin has the opposite logi c value of the suspend pin. the CP2114 exits suspend mode when any of the following occur: resume signaling is detected or generated, a usb reset signal is detected, or a device reset occurs. suspend and suspend are weakly pulled to vio in a high impedance state during a CP2114 reset. if this behavior is undesirable, a strong pulldown (10 k ? ) can be used to ensure suspend remains low during reset. the logic level and output mode (push-pull or open-drain) of various pins during usb suspend is configurable in the prom. see section 9 for more information. 7. asynchronous serial data bus (uart) interfaces the uart interface consists of the tx (transmit) and rx (receive) data signals as well as rts (ready to send) and cts (clear to send) flow control signals. the uart is programmable to support a variety of data formats and baud rates. the data formats and baud rates available are listed in table 20. the baud rate generator for the uart interface is very flex ible, allowing the user to request any baud rate in the range from 300 bps to 1 mbps. if the baud rate cannot be dire ctly generated from the 48 mhz oscillator, the device will choose the closest possible op tion. the actual baud ra te is dictated by e quation 3 and equation 4. equation 3. clock divider calculation equation 4. baud rate calculation most baud rates can be generated with an error of less th an 1.0%. a general rule of thumb for the majority of uart applications is to limit the baud rate error on both the transmitter and the receiver to no more than 2%. the clock table 20. data formats and baud rates data bits 5, 6, 7, and 8 stop bits 1, 1.5 1 , and 2 parity type none, even, odd, mark, space baud rate 300bps to 1mbps 2, 3, 4, 5 notes: 1. 1.5 stop bits only available when using 5 data bits. 2. baud rates above 500,000 baud are not supported with 5 or 6 data bits 3. max of 500 kbaud with flow control, audio playback only 4. max of 230 kbaud with flow control, audio playback and listening 5. with flow control, audio can support higher baud rates, but throughput is greatly reduced. clock divider 48 mhz 2 prescale requested baud rate ? ? ---------------------------------------------------------------------------------------------------- = prescale 4 if requested baud rate 300 bps ? = prescale 1 if requested baud rate 300 bps ? = actual baud rate 48 mhz 2 prescale clock divider ? ? ---------------------------------------------------------------------------- - = prescale 4 if requested baud rate 300 bps ? = prescale 1 if requested baud rate 300 bps ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 24 rev. 1.0 divider value obtained in equation 3 is rounded to the nearest integer, which may produce an error source. another error source will be the 48 mhz oscill ator, which is accurate to 0.25%. knowing the actual and request ed baud rates, the total baud rate error can be found using equation 5. equation 5. baud rate error calculation the uart also supports the transmission of a line break. the length of time for a line break is programmable from 1 to 125 ms, or it can be set to transmit indefinitely until a stop command is sent from the application. 8. gpio pins the CP2114 supports twelve user-configurable gpio pins. each of these gpio pins are usable as inputs, open- drain outputs, or push-pull outputs. all of the pins have alternate functions which are listed in table 21. to use the pin as a gpio, the pin must first be configured for that mode. more information regarding the configuration and usage of these pins is available in ?an721: cp210x/cp21xx device customiz ation guide? availa ble on the silicon labs website. the configuration of the pins is one-t ime programmable for each device. see section 9 for more information about programming the gpio pin functionality. the difference between an open-drain output and a push-pu ll output is when the gpio output is driven to logic high. a logic high, open-drain output pulls the pin to the vi o rail through an internal, pull-up resistor. a logic high, push-pull output directly connects the pin to the vi o voltage. open-drain outputs are typically used when interfacing to logic at a higher voltage than the vio pin. these pins can be safely pulled to the higher, external voltage through an external pull-up resistor. the maximum external pull-up voltage is 5 v. the speed of reading and writing the gpio pins is subjec t to the timing of the usb bus. gpio pins configured as inputs or outputs are not recomm ended for real-time signalling. table 21. gpio alternate functions pin default function alternate function 1 (gpio function) alternate function 2 gpio.0_rmute record mute gpio.0 gpio.1_pmute playback mute gpio.1 gpio.2_vol- volume down gpio.2 gpio.3_vol+ volume up gpio.3 gpio.4_rmuteled record mute led gpio.4 gpio.5_txt_dacsel0 dac se lector 0 gpio.5 tx toggle gpio.6_rxt_dacsel1 dac selector 1 gpio.6 rx toggle gpio.7_rts_dacsel2 dac se lector 2 gpio.7 uart rts gpio.8_cts_dacsel3 dac selector 3 gpio.8 uart cts gpio.9_clkout clock output gpio.9 gpio.10_tx uart tx gpio.10 gpio.11_rx uart rx gpio.11 baud rate error (%) 100 1 actual baud rate requested baud rate ---------------------------------------------------------- - ? ?? ?? ? 0.25% ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 25 8.1. gpio.0-4?audio playback and record the CP2114 includes several audio playback and record signals, such as volume increase, volume decrease, playback mute, and record mute. when connected over usb, the CP2114 can control the host volume settings with these pins via the standard usb hid consumer cont rol interface. on the CP2114 evaluation board, these pins are all connected to buttons. single-pressing the volume increase (gpio.3_vol+) and volume decrease (gpio.2_vol-) butt ons will increase or decrease the volume; holding the button will continue increasing or decreasing the volume. if pl ayback is muted , changing the vo lume with either of these buttons will unmute playback. in addition, there are tw o mute functions implemented as well. single-pressing the record mute (gpio.0_rmute) and the playback mute (gpio.1_pmute) button s will toggle between mute and unmute states. when record is mu ted, the signal gpio.4_rmuteled will be driven low (and illuminate an led on the evaluation board). 8.2. gpio.5-8?dac selection the state of gpio.5 through gpio.8 specify which dac configuration will be loaded after reset. by default, gpio.5, gpio.6, gpio.7, and gpio.8 are all configured for the dac selection functi on (alternate function 1). if the four gpio.5 thro ugh gpio.8 pins are all configured as dac select inputs (their default configuration), the state of these pins specifies which da c configuration will be loaded afte r reset (see table 2 2). the boot dac configuration specif ied by the one-time programmable rom will be used if the state of these dac select pins is 1110b (index 14), or if any of the fo ur gpio.5-8 pins have been configured to something other than dac select. the no dac configuration option (1111b, i.e. index 15) sh ould be used when bringing up a new dac. using this configuration, dac configuration text files can be written to ram and tested until the dac configuration string is finalized. at that point, the configuration string c an be programmed into the one-time programmable rom. dac selection pin mapping is shown in table 22. table 22. dac selection pin mapping index gpio.8 dacsel3 gpio.7 dacsel2 gpio.6 dacsel1 gpio.5 dacsel0 boot dac configuration 00000 config[0]: cs42l55 10001 config[1]: wm8523 20010 config[2]: pcm1774 30011 user-programmed dac configurations 40100 50101 60110 70111 81000 91001 101010 111011 121100 131101 141110boot dac configuration is specified by the one- time programmable rom 151111 no dac configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 26 rev. 1.0 8.3. gpio.5-6?uart tran smit and receive toggle gpio.5 and gpio.6 are configurable as uart transmit to ggle and receive toggle pins. these pins are logic high when a device is not transmitting or receiving data, and t hey toggle at a fixed rate as specified in table 5 when uart data transfer is in progress. typically, these pins are connected to two leds to indicate data transfer. figure 12. transmit and receive toggle typical connection diagram CP2114 gpio.5 ? tx toggle gpio.6 ? rx toggle vio www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 27 8.4. gpio.7-8?hardware fl ow control (rts and cts) to utilize the functionality of the rts and cts pins of the CP2114, the device must be configured to use hardware flow control. rts, or ready to send, is an active-low output from th e CP2114 and indicates to the external uart device that the CP2114?s uart rx fifo has not reached the watermark level and is ready to accept more data. when the CP2114 is processing audio, the watermark level is 2 bytes. when the CP2114 is not processing audio, the watermark is 226 bytes. when the amount of data in t he rx fifo reaches the watermark, the CP2114 pulls rts high to indicate to the external ua rt device to stop sending data. cts, or clear to send, is an active-low input to the cp21 14 and is used by the external uart device to indicate to the CP2114 when the external uart device?s rx fifo is getting full. the CP2114 will not send more than two bytes of data once cts is pulled high. figure 13. hardware flow control typical connection diagram 8.5. gpio.9?clock output gpio.9 is configurable to output a configurable cmos cl ock output. the clock output appears at the pin at the same time the device completes enumeration and exits u sb suspend mode. the clock output is removed from the pin when the device enters usb suspend mode. the output frequency is configurable through the use of a divider and the accuracy is specified in table 6. the output fre quency is 24 mhz when the divider is set to 0 and the system clock is 48 mhz. the output frequency is 24.576 mhz when the divider is set to 0 and the system clock is 49.152 mhz. for divider values between 1 and 255, th e output frequency is determined by the formula: equation 6. gpio.9 clock output frequency CP2114 rs-232 dte tx rx tx rx rts cts gpio.7 ? rts gpio.8 ? cts gpio.9 clock frequency sysclk 2 clockdivider ? ---------------------------------------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 28 rev. 1.0 9. one-time programmable rom the CP2114 has an internal 5.5kb configuration one-ti me programmable rom. there are 2 configuration areas in the one-time programmable rom: 1. global configuration area. this area stores the usb string descriptors and gpio pin configuration. the CP2114 ships with default global configuration settings that allow the CP2114 to be used as-is for customer production. there is also a customer global configuration area that provides customization of the device if desired. 2. audio specific configuration area. this area st ores up to 32 different audio configurations. the configurations set behavior of the CP2114 audio functions as well as configuration data for dacs. the one-time programmable rom is shown in figure 14. note that the CP2114 standard device ships pre- programmed for 3 different dacs, with the desired dac being selected via the dac select pins (dacsel0, dacsel1, dacsel2, dacsel3). additio nal dac support can be added, and c onfiguration of that dac controlled by an one-time programmable rom setting or by the dac select pins. if the programmable rom has not been programmed, the device uses the default confi guration data shown in table 26 and table 27. the configuration data rom can be prog rammed by silicon labs pr ior to shipment with th e desired configuration information. it can also be programmed in-system over the usb interface by adding a capacitor to the pcb. if the configuration rom is to be programmed in-system, a 4.7 f capacitor must be pr esent between the vpp pin and ground. no other circuitry should be connected to vpp during a programming operation, and vio must remain at 3.3 v or higher to successfully write to the configuration rom. figure 14. one-time programmable rom configuration block diagram controller ram config audio dac CP2114 usb eprom i2c usb host dac select pins[0:3] 4 i2s dac configuration & control digital audio signal empty0 empty1 empty2 empty3 empty4 empty31 cs42l55 wm8523 pcm1774 audio config empty default global config customized global config global config area boot index area audio config area www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 29 9.1. audio interface configuration the audio configuration area is used to configure the boot index as well as the audio configuration strings. the boot index determines which of the programmed audio config uration strings will be used after reset. the following sections describe the audio interface in more detail. 9.1.1. audio interface boot configuration process the global configurations are automat ically loaded when the CP2114 powers up. the audio boot configuration depends on the gpio dac select pin settings according to flow chart shown in figure 15. the audio configuration can be set by a one-time programmable rom boot index or by reading the boot index from the dac select pins. setting the dac_select pins to 0x0f will not boot any dac conf iguration. this is need ed for adding support for a new dac. in this case, the silicon labs gui can be used to write the dac settings. after experimentation and testing, the configuration can be written to the one-t ime programmable rom. the one-time programmable rom can be programmed in-system or silicon labs can provid e preprogrammed parts with a customer co nfiguration. figure 15. boot configuration flowchart boot use dac select pins? boot index = dac select pins program dac config over i2c load CP2114 config from eprom boot index = eprom boot index enumerate usb yes no read eprom global config boot index = 0x0e? do not load any audio config boot index = 0x0f? low power suspend waiting for usb traffic no no yes yes www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 30 rev. 1.0 9.1.2. audio configuration string format there are 2 components to the audio configuration of the CP2114: 1. programmability of the CP2114 itself. 2. programmability of the dac. to simplify the configuration of the cp 2114 and the attached dac, a unified configuration string is employed. the first 30 bytes of this configuration string are for the CP2114 audio and control properties. all data after byte 30 is for configuration of the dac. table 23 shows the format of th e configuration string for the CP2114 and attached dac. note also that in the dac configuration part there may be ?in-band? commands. these are special characters that are used to specify delays and are documented in the following sections. in the one-time programmable rom, the audio configurat ion string is preceded by a two-byte length field specifying the total size of the configuration in bytes incl uding the two-byte length field itself. the least significant byte (lsb) of the length field goes first. for example, the audio configuration for th e cs42l55 dac consists of 98- byte configuration. the length field itself is 2-byte long, which makes the total size 100-byte. the audio configuration starts with 0x64, 0x00 followed by the configuration string. the CP2114 configuration program only requires the configuration string. the program will parse the string, calculate th e total length, and insert the length field before sending the request to the device. table 23. audio configuration string byte name description 0 dac_version identifies revision of dac 1 user_defined user can store any info desired here 2 i2c_address specify the dac i2c address www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 31 3 audio_props controls audio properties bit position76543210 bit name mb st i2c_ck i2c_pr drs dvc ljms af mb mute bit. 0: no affect 1: CP2114 will handle mute via mute bits at bytes 12,13,14,15 and 17 st synchronization type 0: asynchronous. will se nd feedback to usb host. 1: synchronous. no feedback to usb host. audio is synchronized via continuous clock adjustment of sample insert/dro p, depending on clock configuration. i2c_ck maximum i2c clock rate supported by the dac. 0: 400 khz 1: 100 khz i2c_pr i2c protocol for read operations. 0: stop 1: repeated start drs dac register size 0: 8 bit 1: 16 bit dvc dac volume control. 0: no volume control supported by dac 1: volume control supported by dac if set, the CP2114 populates volume control in the feature unit usb descriptor. if clear, 0 is specified in volume control to prevent the host from sending set_cur requests. ljms i2s mode. only applies if using left justified format. 0: 16bit left justified mode. 1: 24bit left justified mode af audio format 0: i2s format 1: left justified format 4 min_volume minimum volume in db, 8-bit signed. this corresponds to the volume control attri- bute min in usb audio spec. 5 max_volume maximum volume in db, 8-bit signed. this corresponds to the volume control attri- bute max in usb audio spec. 6 vol_step volume step counts per db. for instance, if volume resolution is 0.25 db, 4 shall be written. a computed res is returned in response to volume control attribute query of res from the host. table 23. audio configuration string byte name description www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 32 rev. 1.0 7 system_props system properties bit position76543210 bit names dmmf are svrp vur ucs scs sf acr dmmf dac min/max register format. 0: unsigned 1: signed are analog record enabled 0: disable 1: enable svrp secondary volume registers polarity. 0: secondary volume registers have same polarity as primary registers 1: secondary volume registers have opposite polarity as primary registers. if only line out is present on the dac, primar y shall be line out; if only headphone is present, primary shall be headphone. if both line out and headphone are present on the dac, either can be designated as primary. CP2114 updates either or both registers when the host changes volume. some dacs may require a separate bit as a ?take into effect immediately? bit. vur volume update registers. some dacs requ ire a specific register is written for vol- ume updates to take effect. 0: dac has no volume update registers. 1: dac has volume update registers. ucs usb clock source 0: usb clock uses internal oscillator 1: usb clock uses external oscillator scs system clock source. note: audio cl ocks will be driven from this source. 0: audio uses internal oscillator 1: audio uses external oscillator sf system frequency 0: 48mhz 1: 49.152mhz acr audio clock ratio. this is the mclk/lrck ratio. 0: 250 1: 256 8 dpvcl dac primary volume control left channel register address. 9 dpvcr dac primary volume control right channel register address. 10 dsvcl dac secondary volume control left channel register address. 11 dsvcr dac secondary volume control right channel register address. 12 dpmblc dac primary mute bit left chan nel register address. ignored if mb=0. 13 dpmbrc dac primary mute bit right channel register address. ignored if mb=0. 14 dsmblc dac secondary mute bit left channel register address. ignored if mb=0. 15 dsmbrc dac secondary mute bit right channel register address. ignored if mb=0. table 23. audio configuration string byte name description www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 33 16 dvcb dac volume control bits start position and bits count. some dac volume registers have limited sign ificant bits. this field lets the signifi- cant bits be specified. for example if the volume registers use only bit [6:0] you would set volume_bit_count=7 and volume_bit_start=0. bit position76543210 bit name vbc vbs vbc volume bit count. specifies number of significant bits for the volume registers vbs volume bits start. specifies the start position of the volume significant bits. 17 dmbp dac mute bit positions. bit position76543210 bit name dmbpl dmbpr dmbpl dac mute bit position left channel. ignored if mb=0. dmbpr dac mute bit position right channel. ignored if mb=0. 18 dvmv dac value minimum volume. specifies the value needed for minimum volume from the dac 19 dvxv dac value maximum volume. specifies the value needed for maximum volume from the dac 20 dvubp dac volume update bit position. ignored vur=0. bit position76543210 bit name dvubpl rcubp dvubpl dac volume update bit position left channel rcubp dac volume update bi t position right channel 21 dpvurl dac primary volume update register left channel register address. ignored f vur=0. 22 dpvurr dac primary volume update register right channel register address. ignored f vur=0. 23 dsvurl dac secondary volume update register left channel register address. ignored f vur=0. 24 dsvurr dac secondary volume update register right channel register address. ignored f vur=0. table 23. audio configuration string byte name description www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 34 rev. 1.0 25 dmp1 dac mute property 1 bit position76543210 bit name gpion x x swm mbg gpion gpio number (0..11) used for dac mute. ignored of mbg=0. swm gpio state when muted. ignored of mbg=0. 0: muted when gpio is low 1: muted when gpio is high. mbg mute by gpio. 0: do not use gpio for mute. 1: use gpio for mute. 26 dmp2 dac mute property 2 bit position76543210 bit namexxxxxxmbzmbvr mbz mute by zeros. 0: do not mute by sending 00?s to the dac 1: mute by sending 00?s to the dac. this is useful for a dac that does not support hardware mute or volume functions. not supported when playback and record are both active. mbvr mute by volume register. 0: do not mute via the volume register. 1: mute via the volume register. some dacs mute by sending a specif ic value to the volume register. 27 dvmv dac volume mute value. mute by sending this value to the volume registers. ignored if mbvr=0. 28 reserved reserved 29 reserved reserved 30-xx dac config start of dac config uration string and ?in-band? commands table 23. audio configuration string byte name description www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 35 9.1.3. dac configuration string starting at byte 30, a dac configuration string is used to communicate with the dac over the i2c interface. if the dac register size bit is 0 (indicating 8-bit mode), the dac register/value pairs should be written in the format of: byte[30] = byte[31] = byte[32] = byte[33] = ... if the dac register size bit is 1 (indicating 16-bit mode), the dac register/value pairs should be written in the format of: byte[30] = byte[31] = byte[32] = byte[33] = byte[34] = byte[35] = ... 9.1.4. dac configuration in-band commands to support special functions such as gpio outputs, arbitrary delay in between dac register access, dac power off sequence in suspend and power on sequence in active mode, the CP2114 supports special in-band commands starting from byte 30. these commands are identified by command codes 0xfa to 0xff. when parsing dac register/value pairs, if CP2114 firmware encounters 0xfa to 0xff in the field, the CP2114 performs the task associated with th e command instead of sending it to the dac. ?? suspend_sequence specifies a sequen ce of dac register/value pairs/tr iplets to power down certain blocks on the dac in suspend mode to minimize power consumption. ?? active_sequence specifies a sequence of dac register/v alue pairs/triplets to power up certain blocks on the dac in active mode. ?? the delay_microseconds, set_gpio and delay_ milliseconds in-band commands can be embedded in suspend_sequence an d active_sequence if needed. ?? set_gpio sets a specified gpio to high or low. ?? delay_microseconds instructs the firmware to in troduce a coarse delay of n microseconds as specified in the parameter list. sim ilarly, delay_milliseconds instru cts the firmware to introduce a course delay in milliseconds. the format of most in-band commands exce pt for suspend_sequence and active_sequence is analogous to dac register/value pairs/triplets. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 36 rev. 1.0 the combination of set_gpio in-band commands and de lay commands can be used to send pulses or toggle output gpios (assuming that these gpios have been co nfigured as output pins). some dacs may require dac reset via a gpio pin, this can be accomplished with in-band commands as well. 9.1.5. dac initialization the dac configuration string should configure the dac to initialize with muted play back. dac volume registers should be set to minimum. this allows CP2114 to synchronize with the host at startup. table 24. dac configuration in-band commands name identifier in-band parameter list dac register size = 0 (8bit) in-band parameter list dac register size = 1(16bit) suspend_ sequence 0xfa ? active_ sequence 0xfb ? reenumer- ate 0xfc delay_ microsec- onds 0xfd set_gpio 0xfe ( << 7 | & 0x0f) ( << 7 | & 0x0f) delay_mill iseconds 0xff www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 37 9.1.6. example CP2114 configuration string as can be seen in the audio configuration string format, a number of fields are dedicated to defining how the dac volume and mute function are implemen ted in the dac. this is needed for the CP2114 to properly scale the volume from db to dac register values using a linear equation and send volume and mute messages from the host to the dac. as an example of CP2114 configuration string, table 25 shows the configuration string in one-time programmable rom as shipped for the cs42l55 codec. table 25. cs42l55 configuration string byte value description 0 01 dac version = 01. this can simply be an identifier for the configuration 1 00 user byte ? any purpose 2 94 i2c address of this dac is 0x94 3 a6 mb = 1 mute is handled with this dac. st = 0. use asynchronous mode?provide feedback to the host. i2c_ck = 1. use 100 khz i2c clock. i2c_pr = 0. i2c uses stop bit. drs = 0. dac has 8bit registers. dvc = 1. dac volume control is supported ljms = 1. 24bit left justified mode is used. af = 0. left justified format is used. 4 c4 minimum volume value for the dac is 0xc4 = -60db. 5 0c maximum volume for the dac is 0x0c = 12db 6 01 volume step per db is 1. 7 e0 dmmf = 1. dac min/max registers are signed. are = 1. analog record is enabled. svrp = 1. secondary volume registers have opposite polarity as primary registers. vur = 0. dac does not have volume update (take effect) registers. ucs = 0. usb clock uses internal oscillator. scs = 0. system clock uses internal oscillator. sf = 0. system frequency is 48 mhz. acr = 0. audio clock ration (mclk/lrck) is 250. 8 1c dpvl = 0x1c. dac primary volume control left channel register address is 0x1c 9 1d dpvr = 0x1d. dac primary volume contro l right channel register address is 0x1d 10 1a dsvl = 0x1a. dac secondary volume control left channel register address is 0x1a 11 1b dsvr = 0x1b. dac secondary volume contro l right channel register address is 0x1b 12 1c dpmblc = 0x1c. dac primary mute bit left channel register address is 0x1c 13 1d dpmbrc = 0x1d dac primary mute bit right channel register address is 0x1d 14 1a dsmblc = 0x1a. dac secondary mute bit left channel register address is 0x1a 15 1b dsmbrc = 0x1b. dac secondary mute bit right channel register address is 0x1b 16 70 dvcb = 0x70. vbc = 7. volume register has 7 significant bits. vbs = 0. volume control starts at bit 0. 17 77 dmbp = 0x77. dmbpl = 7. dac mute bit position left channel is bit 7 dmbpr = 7. dac mute bit position right channel is bit 7 www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 38 rev. 1.0 18 44 dvmv = 0x44. dac value for minimum volume is 0x44. 19 0c dvxv = 0x0c. dac value fo r maximum volume is 0x0c. 20 00 na - no volume update register. 21 00 na - no volume update register. 22 00 na - no volume update register. 23 00 na - no volume update register. 24 00 na - no volume update register. 25 00 na. mbg = 0. no mute by gpio. 26 00 mbz = 0. do not mute by sending 00?s. mbvr = 0. do not mute but volume register. 27 00 dvmv = 0. do not mute by sending value to register. 28 00 reserved 29 00 reserved table 25. cs42l55 configuration string byte value description www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 39 9.2. usb and gp io configuration the global configuration area is used to store usb desc riptors and gpio configuratio n. if the programmable rom has not been programmed, the default configuration data shown in table 26, table 27, and table 28 is used. in addition, each field in table 26, table 27, and table 28 may only be customized once. while customization of the usb configuration data is op tional, customizing the vid/pid combination is strongly recommended. a unique vid/ pid will prevent the device from being recognized by any ot her manufacturer?s software application. a vendor id c an be obtained from www.usb.org or silicon labs can provide a free pid for the oem product that can be used with t he silicon labs vid. all CP2114 device s are pre-program med with a unique serial number. it is important to have a unique serial if it is possible for multiple CP2114-based devices to be connected to the same pc. table 26. default usb configuration data name value vendor id 10c4h product id eab0h power descriptor (attributes) 80h (bus-powered) power descriptor (max. power) 32h (100 ma) release number 0100h (release version 01.00) manufacturer string ?silicon laboratori es? (62 ascii characters maximum) product description string ?CP2114 usb- audio bridge? (62 characters maximum) serial string unique 8 character ascii string (30 characters maximum) table 27. default gpio data pin name default function gpio.0_rmute record mute gpio.1_pmute playback mute gpio.2_vol- volume down gpio.3_vol+ volume up gpio.4_rmuteled record mute led gpio.5_txt_dacsel0 dac selector 0 gpio.6_rxt_dacsel1 dac selector 1 gpio.7_rts_dacsel2 dac selector 2 gpio.8_cts_dacsel3 dac selector 3 gpio.9_clkout clock output gpio.10_tx uart tx gpio.11_rx uart rx table 28. default uart and suspend data name default function flush buffers flush tx and rx fifo on open suspend output?push pull suspend output?push pull suspend latch 0x0000 suspend mode 0x0000 clock divider divide by 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 40 rev. 1.0 10. voltage regulator the CP2114 includes an on-chip voltage regulator with a 3.45 v output. this allows the CP2114 to be configured as either a usb bus-powered device or a usb self-power ed device. a typical connection diagram of the device in a bus-powered application using the regulator is shown in figure 16. when enabled, the voltage regulator output appears on the vdd pin and can be used to power external devices. see table 4 for the voltage regulator electrical characteristics. if it is desired to use the regulato r to provide vdd in a self-powered application, the same connections from figure 16 can be used, but connect regin to an on-board 5 v supply, and disconnect it from the vbus pin. figure 16. typical bus-powered connection diagram note 3 suspend signals uart CP2114 gpio.7_rts_dacsel2 gpio.8_cts_dacsel3 gpio.9_clkout gpio.5_txt_dacsel0 gpio.6_rxt_dacsel1 vpp suspend suspend gpio.10_tx gpio.11_rx rst vio 4.7 k note 4 note 1 : avalanche transient voltage suppression diodes compatible with full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. note 2 : vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. note 3 : an external pull-up is not required, but can be added for noise immunity. note 4 : if configuration rom is to be programmed via usb, a 4.7 ? f capacitor must be added between vpp and ground. during a programming operation, the pin should not be connected to other circuitry, and vio must be at least 3.3 v. 4.7 ? f gpio.0_rmute gpio.1_pmute gpio.2_vol- gpio.3_vol+ gpio.4_rmuteled i2s and i2c signals to dac lrck sdin sdout extclk sda scl sck note 2 note 1 vbus d+ d- gnd usb connector regin vdd gnd vio vbus d+ d- 1 ? f 1-5 ? f 0.1 ? f 3.45 v power volume/ mute controls dac selector clock output (optional) clock input (optional) mclk www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 41 alternatively, if 3.0 to 3.6 v power source is supplied to the vdd pin, the CP2114 can function as a usb self- powered device with the voltage regulator bypassed. for th is configuration, the regin input should be tied to vdd to bypass the voltage regulator. a typical connection diag ram showing the device in a self-powered application with the regulator bypassed is shown in figure 17. the usb max power and power attributes descriptor must match the device power usage and configuration. see application note ?an721: cp210x/cp21xx device customization guide? for in formation on how to customize usb descriptors for the CP2114. figure 17. typical self-powered connection diagram (regulator bypass) CP2114 note 2 note 1 vbus d+ d- gnd usb connector vdd regin gnd vio vbus d+ d- 0.1 ? f 1-5 ? f note 1 : avalanche transient voltage suppression diodes compatible with full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. note 2 : vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. note 3 : an external pull-up is not required, but can be added for noise immunity. note 4 : if configuration rom is to be programmed via usb, a 4.7 ? f capacitor must be added between vpp and ground. during a programming operation, the pin should not be connected to other circuitry, and vio must be at least 3.3 v. 3.3 v power note 3 suspend signals uart gpio.7_rts_dacsel2 gpio.8_cts_dacsel3 gpio.9_clkout gpio.5_txt_dacsel0 gpio.6_rxt_dacsel1 vpp suspend suspend gpio.10_tx gpio.11_rx rst vio 4.7 k note 4 4.7 ? f gpio.0_rmute gpio.1_pmute gpio.2_vol- gpio.3_vol+ gpio.4_rmuteled i2s and i2c signals to dac lrck sdin sdout extclk sda scl sck volume/ mute controls dac selector clock output (optional) clock input (optional) mclk www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 42 rev. 1.0 11. CP2114 interface specificati on and windows interface dll the CP2114 is a usb human interface device (hid), an d as most operating systems include native hid drivers, custom drivers do not need to be installed. the CP2114 doe s not fit one of the standard hid device types, such as a keyboard or mouse, and any CP2114 pc application needs to use the CP2114?s hid specification to communicate with the device. the low-level hid specif ication for the CP2114 is provided in ?an433: cp2110/ CP2114 hid interface specification.? this document descri bes all of the basic functions for opening, reading from, writing to, and closing the device, as well as the rom programming functions. a windows dll that encapsulates the CP2114 hid interfac e and also adds higher level features such as read/ write time-outs is provided by silic on labs. this dll is the recommended in terface for the CP2114. the windows dll is documented in CP2114 windows dll specification. both of these documents and the dll are available online at http://www.silabs.com/ . 12. relevant ap plication notes the following application notes are applicable to the cp 2114. the latest versions of these application notes and their accompanying software are available at http://www.silabs.com/appnotes . ?? an721: cp210x/cp21xx device customization guide . this application note describes how to use the an721 software cp21xxsetids to configure t he usb parameters on the cp21xx devices. ?? an433: cp2110/CP2114 hid to uart api specification . this application note describes how to interface to the CP2114 using the windows interface dll and the max os-x dylib. www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 rev. 1.0 43 n otes : www.datasheet.net/ datasheet pdf - http://www..co.kr/
CP2114 44 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories, silicon labs, and usbxpre ss are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in a ll respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims respons ibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratories assumes no re sponsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its pr oducts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages. www.datasheet.net/ datasheet pdf - http://www..co.kr/

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